Semiconductor device test method and semiconductor device

ABSTRACT

A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2010-064507, filed on Mar. 19,2010, the entire contents of which are incorporated herein by reference.

FIELD

The embodiment discussed herein is directed to a semiconductor devicetest method and a semiconductor device.

BACKGROUND

One of operation tests of the semiconductor device is a transition delaytest (TDT) evaluating a delay. In the transition delay test, a signalpattern to generate a signal change upon application of clock is set inflip-flops in the semiconductor device that is a test object by a scanshift or the like, and two pulses (clocks) at high speed are appliedfrom an external part. The clock application for the first timegenerates a signal change and the clock application for the second timecaptures the changed signal in an arbitrary flip-flop. By comparing anddetermining whether the captured changed signal coincides with anexpected value, the determination whether the delay in the semiconductordevice satisfies the condition as non-defective or not is performed.More specifically, in the transition delay test, when the changed signalcoincides with the expected value, the semiconductor device isdetermined as non-defective, whereas when the changed signal does notcoincide with the expected value, the semiconductor device is determinedas defective. Causes of occurrence of defective include various onessuch as the switching noise, the configuration of design for test (DFT),the measurement circumference, the transistor characteristics and so on.

Further, a semiconductor device in which a power supply noisemeasurement cell composed of a MOS transistor having a gate connected toa power supply noise measurement point in the semiconductor device, asource connected to a determination reference voltage supply terminal,and a drain connected to a measurement terminal is installed to enablemeasurement of the power supply noise is proposed. This semiconductordevice supplies the determination reference voltage to the source viathe determination reference voltage supply terminal and monitors, at themeasurement terminal, the change in the drain current with respect tovariation in a gate-source voltage or the change of the ON/OFF stateaccording to the power supply noise to measure the power supply noise(see, for example, Patent Document 1).

-   [Patent Document 1] Japanese Laid-open Patent Publication No.    2004-184345

In the transition delay test, the test is conducted while thesemiconductor device operates under conditions more strict than theactual use conditions such that the signal changes are generated in theflip-flops in the semiconductor device at the same time. In other words,the transition delay test is conducted while a number of flip-flops thatis nearly impossible under the actual use conditions operate at the sametime. Therefore, when the transition delay test is conducted in alarge-size semiconductor device having a huge number of flip-flops, thesemiconductor device may be determined, due to the influence of thegenerated noise, as defective which will be determined as non-defectivewithout the influence of the noise. In other words, the delay increasesdue to the influence of the power supply noise (a drop of the powersupply voltage) generated by the operation (switching relating to thesignal change) or the like of the huge number of flip-flops, with theresult that the semiconductor device may be determined as defective.

SUMMARY

According to an aspect of the embodiment, provide is a semiconductordevice test method, including: conducting a determination test of a testobject circuit in a semiconductor device divided into a plurality ofcircuit blocks, while changing concurrently operating circuit blocks;detecting a power supply noise generated in the semiconductor deviceduring conduction of the determination test; determining a circuit scalerelating to conduction of an operation test based on a result of theconducted determination test and the detected power supply noise; andperforming the operation test on the test object circuit controllingclocks to be supplied to the circuit blocks so that the circuit scale ofthe concurrently operating circuit blocks does not exceed the determinedcircuit scale.

The object and advantages of the embodiment will be realized andattained by means of the elements and combinations particularly pointedout in the claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the embodiment, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating a configuration example of a testsystem of a semiconductor device in an embodiment;

FIG. 2 is a diagram illustrating a configuration example of a detectioncircuit of the semiconductor device in this embodiment;

FIG. 3A to FIG. 3C are diagrams illustrating examples of a clock controlcircuit of the semiconductor device in this embodiment;

FIG. 4A and FIG. 4B are diagrams illustrating another example of theclock control circuit of the semiconductor device in this embodiment;

FIG. 5 is a flowchart illustrating an example of a semiconductor devicetest method in this embodiment; and

FIG. 6 is a chart illustrating voltage levels of a comparison voltageand an example of a power supply determination waveform.

DESCRIPTION OF EMBODIMENTS

Hereinafter, an embodiment will be described based on the drawings.

FIG. 1 is a block diagram illustrating a configuration example of a testsystem of a semiconductor device in an embodiment. Note that FIG. 1illustrates only elemental features for conducting a transition delaytest in the test system of the semiconductor device in this embodiment.

In FIG. 1, numeral 10 denotes a testing device (tester) of asemiconductor device, and numeral 20 denotes a semiconductor device as atest object device (for example, a chip on which a test object circuitis mounted).

The testing device 10 has a control part 11, a signal generation part12, and a signal processing part 13.

The control part 11 controls functional parts in the testing device 10.The control part 11 is composed of, for example, a CPU (CentralProcessing Unit), memory and so on, and the CPU reads out a programstored in the memory or the like and executes the program to therebycontrol the functional parts to conduct the transition delay test of thesemiconductor device 20.

The signal generation part 12 generates various signals to be suppliedto the semiconductor device 20 and outputs the signals according to thecontrol by the control part 11. The various signals to be supplied tothe semiconductor device 20 include a control signal controlling a clockto be supplied to an internal circuit of the semiconductor device 20, acontrol signal for acquiring the level of the power supply noise, asignal for setting a signal pattern to conduct the transition delay testin the internal circuit of the semiconductor device 20 and so on.

The signal processing part 13 performs predetermined signal processingin response to the signal from the semiconductor device 20 and outputsprocessing result to the control part 11. The signal processing part 13,for example, receives a signal that has been subjected to signal changein the transition delay test, and compares whether the changed signalcoincides with an expected value or not to determine the result (OK orNG) of the transition delay test, and outputs the determination to thecontrol part 11.

The semiconductor device 20 has an internal circuit 21, a clock controlcircuit 22, and a detection circuit 23. To the functional parts(including the internal circuit 21, the clock control circuit 22, andthe detection circuit 23) in the semiconductor device 20, a power supplyvoltage (Vcc) and a reference potential (GND) are supplied from thetesting device 10.

The internal circuit 21 is a circuit which includes flip-flops, logiccircuits and so on and implements a predetermined function in thesemiconductor device 20. The internal circuit 21 is a circuit that isthe test object of the transition delay test. When conducting thetransition delay test, a signal pattern to generate signal change uponapplication of clock is set in the flip-flops of the internal circuit 21by scan shift or the like based on the signal from the testing device10. Thereafter, a clock for the first time for generating a signalchange and a clock for the second time for capturing the changed signalin an arbitrary flip-flop are applied to the internal circuit 21.

In this embodiment, the internal circuit 21 is divided into five circuitblocks such that the numbers of the flip-flops included in the blocksare substantially equal (such that each circuit scale is substantiallyequal), and the five circuit blocks are referred to as circuit blocks21-a, 21-b, 21-c, 21-d, 21 e, respectively. More specifically, theinternal circuit 21 is divided such that each of the circuit blocks 21-ato 21-e has flip-flops corresponding to 20% of the total number offlip-flops existing in the internal circuit 21. In this embodiment, thetransition delay test can be conducted taking the divided circuit block21-a, 21-b, 21-c, 21-d, 21-e as a unit.

The clock control circuit 22 is supplied with the clock (CLK) and thecontrol signal from the testing device 10. The clock control circuit 22controls the clock to be supplied to the internal circuit 21 (morespecifically, each of the circuit blocks 21-a, 21-b, 21-c, 21-d, 21-e)based on the supplied control signal when conducting the transitiondelay test.

The detection circuit 23 is supplied with the control signal and thereference power supply (corresponding to Vcc without power supply noise)and supplies measurement result of the power supply noise to the testingdevice 10. The detection circuit 23 performs monitoring of the powersupply noise by comparing voltage levels of a predetermined comparisonvoltage generated based on the reference power supply and the powersupply voltage (Vcc), and outputs the result (the level of the powersupply noise) to the testing device 10.

FIG. 2 is a block diagram illustrating a configuration example of thedetection circuit 23 of the semiconductor device 20. The detectioncircuit 23 has a determination part 31, a register 33, a comparison part34, and a storage part 35.

The determination part 31 has comparators 32-A, 32-B, 32-C, 32-D, 32-Eand resistors R1, R2, R3, R4, R5, R6. The resistors R1, R2, R3, R4, R5,R6 are connected in series in this order between a power supply line towhich the reference power supply is supplied from the testing device 10and the reference potential GND. Further, each of the comparators 32-Ato 32-E has one input connected to a power supply line to which thepower supply voltage (Vcc) is supplied from the testing device 10 andanother input connected to an interconnection point of the respectiveresistors R1, R2, R3, R4, R5, R6 connected in series.

More specifically, to one input of each of the comparators 32-A to 32-E,the power supply voltage (Vcc) is supplied. Further, the other input ofthe comparator 32-A is connected to a connection point of the resistorsR1 and R2, and the potential at the connection point (referred to as avoltage level A) is inputted to the other input of the comparator 32-A.Similarly, the other input of the comparator 32-B is connected to aconnection point of the resistors R2 and R3, and the potential at theconnection point (referred to as a voltage level B) is inputted to theother input of the comparator 32-B. The other input of the comparator32-C is connected to a connection point of the resistors R3 and R4, andthe potential at the connection point (referred to as a voltage level C)is inputted to the other input of the comparator 32-C. The other inputof the comparator 32-D is connected to a connection point of theresistors R4 and R5, and the potential at the connection point (referredto as a voltage level D) is inputted to the other input of thecomparator 32-D. The other input of the comparator 32-E is connected toa connection point of the resistors R5 and R6, and the potential at theconnection point (referred to as a voltage level E) is inputted to theother input of the comparator 32-E.

Here, the voltage levels A to E will be explained with reference to FIG.6. FIG. 6 illustrates the voltage levels A to E and an example of apower supply determination waveform.

In this embodiment, if the voltage level of the power supply voltagewhen the voltage drops due to the influence of the power supply noisegenerated when the transition delay test is conducted is higher than thevoltage level A, the test can be conducted on 100% of the total numberof flip-flops included in the internal circuit 21. If the voltage levelof the power supply voltage when the voltage drops is between thevoltage level A and the voltage level B, the test can be conducted on80% of the total number of flip-flops included in the internal circuit21, and the test is conducted with the internal circuit 21 beingn-divided by the number of 80% or less of the total number offlip-flops. Further, if the voltage level of the power supply voltagewhen the voltage drops is between the voltage level B and the voltagelevel C, the test can be conducted on 60% of the total number offlip-flops included in the internal circuit 21, and the test isconducted with the internal circuit 21 being n-divided by the number of60% or less of the total number of flip-flops. If the voltage level ofthe power supply voltage when the voltage drops is between the voltagelevel C and the voltage level D, the test can be conducted on 40% of thetotal number of flip-flops included in the internal circuit 21, and thetest is conducted with the internal circuit 21 being n-divided by thenumber of 40% or less of the total number of flip-flops. Further, if thevoltage level of the power supply voltage when the voltage drops isbetween the voltage level D and the voltage level E, the test can beconducted on 20% of the total number of flip-flops included in theinternal circuit 21, and the test is conducted with the internal circuit21 being n-divided by the number of 20% or less of the total number offlip-flops. For example, in the power supply determination waveformexemplified in FIG. 6, since the voltage level of the power supplyvoltage when the voltage drops most is between the voltage level B andthe voltage level C, the test is conducted with the internal circuit 21being n-divided by the number of 60% or less of the total number offlip-flops. Note that the resistance values of the resistors R1 to R6are set so that the voltage levels A to E take the aforementionedvoltages.

The register 33 is supplied with the outputs of the comparators 32-A,32-B, 32-C, 32-D, 32-E included in the determination part 31 and holdsthe outputs. The comparison part 34 compares a table (a standard table)stored in the storage part 35 in advance to the value held in theregister 33, and outputs a result to the testing device 10 based on thecomparison result. By outputting the comparison result to the tablestored in advance to the testing device 10, the signal amount necessaryfor information transmission can be reduced as compared to the casewhere the output of each of the comparators 32-A to 32-E as it is to thetesting device 10. Note that there is a sufficient transmission bandbetween the testing device 10 and the detection circuit 23 of thesemiconductor device 20, the output of each of the comparators 32-A to32-E included in the determination part 31 may be outputted to thetesting device 10 as it is.

FIG. 3A and FIG. 3B are diagrams for explaining examples of the clockcontrol circuit 22 of the semiconductor device 20. FIG. 3A and FIG. 3Beach illustrate the clock control circuit 22 supplying clocks to thecircuit blocks 21-a, 21-b, 21-c, 21-d, 21-e while not interrupting theclocks but adjusting (shifting) the phases thereof.

FIG. 3A is a block diagram illustrating a configuration example of theclock control circuit 22. In FIG. 3A, numerals 41-a, 41-b, 41-c, 41-d,41-e denote delay devices each delaying the inputted signal by apredetermined delay amount and outputting it, and the clocks (CLK) fromthe testing device 10 are inputted into the delay devices. When thedelay amount of the delay device 41-a is Z1, the delay amount of thedelay device 41-b is Z2, the delay amount of the delay device 41-c isZ3, the delay amount of the delay device 41-d is Z4, and the delayamount of the delay device 41-e is Z5, the delay amounts Z1, Z2, Z3, Z4,Z5 are different from one another. Further, each of the delay amountsZ1, Z2, Z3, Z4, Z5 is shorter than one cycle of the inputted clock(CLK).

Further, numerals 42-a, 42-b, 42-c, 42-d, 42-e denote selectors forsupplying clocks to the corresponding circuit blocks 21-a, 21-b, 21-c,21-d, 21-e. The selector 42-a, into which the clock (CLK) and the outputof the delay device 41-a are inputted, selects one of the clock (CLK)and the output of the delay device 41-a based on the control signal CTLfrom the testing device 10 and outputs the selected one to the circuitblock 21-a. The selector 42-b, into which the clock (CLK) and the outputof the delay device 41-b are inputted, selects one of them based on thecontrol signal CTL and outputs the selected one to the circuit block21-b. The selector 42-c, into which the clock (CLK) and the output ofthe delay device 41-c are inputted, selects one of them based on thecontrol signal CTL and outputs the selected one to the circuit block21-c. The selector 42-d, into which the clock (CLK) and the output ofthe delay device 41-d are inputted, selects one of them based on thecontrol signal CTL and outputs the selected one to the circuit block21-d. The selector 42-e, into which the clock (CLK) and the output ofthe delay device 41-e are inputted, selects one of them based on thecontrol signal CTL and outputs the selected one to the circuit block21-e.

In other words, the selector 42-a outputs the clock (CLK) or a clock (adelayed clock) made by delaying the clock (CLK) by the delay amount Z1as a clock (CLK:a) to the circuit block 21-a. The selector 42-b outputsthe clock (CLK) or a clock made by delaying the clock (CLK) by the delayamount Z2 as a clock (CLK:b) to the circuit block 21-b. The selector42-c outputs the clock (CLK) or a clock made by delaying the clock (CLK)by the delay amount Z3 as a clock (CLK:c) to the circuit block 21-c. Theselector 42-d outputs the clock (CLK) or a clock made by delaying theclock (CLK) by the delay amount Z4 as a clock (CLK:d) to the circuitblock 21-d. The selector 42-e outputs the clock (CLK) or a clock made bydelaying the clock (CLK) by the delay amount Z5 as a clock (CLK:e) tothe circuit block 21-e.

FIG. 3B is a block diagram illustrating another configuration example ofthe clock control circuit 22. In FIG. 3B, numerals 43-a, 43-b, 43-c,43-d, 43-e denote delay devices each delaying the inputted signal by apredetermined delay amount and outputting it, and the clock (CLK) fromthe testing device 10 is inputted into each of the delay devices. Thedelay device 43-a outputs its output to the circuit block 21-a as theclock (CLK:a), and the delay device 43-b outputs its output to thecircuit block 21-b as the clock (CLK:b). The delay device 43-c outputsits output to the circuit block 21-c as the clock (CLK:c), and the delaydevice 43-d outputs its output to the circuit block 21-d as the clock(CLK:d). The delay device 43-e outputs its output to the circuit block21-e as the clock (CLK:e).

Here, the delay amounts Z1, Z2, Z3, Z4, Z5 of the delay devices 43-a,43-b, 43-c, 43-d, 43-e are independently controlled by the controlsignals CTL from the testing device 10. The delay amounts Z1, Z2, Z3,Z4, Z5 are delay amounts each shorter than one cycle of the inputtedclock (CLK), and they may be different from one another or a part or allof them may be the same.

The clock control circuit 22 illustrated in each of FIG. 3A or FIG. 3Bcan supply clocks to the circuit blocks 21-a, 21-b, 21-c, 21-d, 21-ewhile not interrupting the clocks but shifting the phases thereof asnecessary. For example, in FIG. 3A, the selectors 42-a to 42-e selectthe outputs of the corresponding delay devices 41-a to 41-e to therebyperform phase adjustment, so that the clocks can be supplied to thecircuit blocks 21-a to 21-e with the phases thereof being made differentfrom one another as illustrated in FIG. 3C. Further, for example, bymaking the delay amounts of the delay devices 43-a to 43-e differentfrom one another in FIG. 3B, the clocks can be supplied to the circuitblocks 21-a to 21 e with phases thereof being made different from oneanother as illustrated in FIG. 3C.

FIG. 4A and FIG. 4B are diagrams for explaining another example of theclock control circuit 22 of the semiconductor device 20. FIG. 4Aillustrates the clock control circuit 22 configured to controlsupply/interruption of the clocks to the circuit blocks 21-a, 21-b,21-c, 21-d, 21-e by employing a so-called gated clock technique.

FIG. 4A is a block diagram illustrating a configuration example of theclock control circuit 22. In FIG. 4A, numerals 51-a, 51-b, 51-c, 51-d,51-e denote gate circuits each of which is composed of a logical productoperation circuit (an AND circuit) in the example illustrated in FIG.4A. Each of the gate circuits 51-a to 51-e, into which the clock (CLK)and the control signal CTL from the testing device 10 are inputted,switches whether to output (supply) or not (interrupt) the clock (CLK)according to the control signal CTL. In short, when the AND circuit isused as the gate circuit as illustrated in FIG. 4A, the clock will beoutputted when the control signal CTL is true, whereas the clock will beinterrupted when the control signal CTL is false.

The gate circuit 51-a outputs its output to the circuit block 21-a asthe clock (CLK:a), and the gate circuit 51-b outputs its output to thecircuit block 21-b as the clock (CLK:b). The gate circuit 51-c outputsits output to the circuit block 21-c as the clock (CLK:c), and the gatecircuit 51-d outputs its output to the circuit block 21-d as the clock(CLK:d). The gate circuit 51-e outputs its output to the circuit block21-e as the clock (CLK:e).

The clock control circuit 22 illustrated in FIG. 4A can be used tocontrol supply and interruption of the clocks to the circuit blocks21-a, 21-b, 21-c, 21-d, 21-e. For example, in FIG. 4A, the controlsignals CTL supplied to the gate circuits 51-a, 51-b, 51-c are set to betrue and the control signals CTL supplied to the gate circuits 51-d,51-e are set to be false. Thereafter, the control signals CTL suppliedto the gate circuits 51-a, 51-b, 51-c are set to be false and thecontrol signals CTL supplied to the gate circuits 51-d, 51-e are set tobe true. Such a control makes it possible to supply the clocks only tothe circuit blocks 21-a, 21-b, 21-c and then supply the clocks only tothe circuit blocks 21-d, 21-e as illustrated in FIG. 4B.

A semiconductor device test method in this embodiment will be explainednext.

FIG. 5 is a flowchart illustrating an example of a semiconductor devicetest method in this embodiment.

When operation is started, the testing device 10 first inputs aflip-flop number calculation signal into the semiconductor device 20that is the test object (S1). For example, the testing device 10generates the flip-flop number calculation signal in the signalgeneration part 12 based on the control by the control part 11, andoutputs it to the semiconductor device 20. Note that the flip-flopnumber calculation signal is a signal similar to the signal inputtedwhen the transition delay test is conducted concurrently in the wholesemiconductor device 20 without limiting the number of concurrentlyoperating flip-flops (the circuit scale) in the semiconductor device 20.

Next, the testing device 10 judges whether the transition delay test ineach circuit scale can be conducted or not in the internal circuit 21 ofthe semiconductor device 20 (S2 to S4). In this event, the testingdevice 10 outputs the control signal to the clock control circuit 22 inthe semiconductor device 20 to change the control signal so that thenumber of concurrently operating flip-flops increase in sequence (thecircuit scale on which test is conducted becomes larger in sequence),and judges whether the transition delay test can be conducted in each ofthe circuit scales or not.

More specifically, the testing device 10 conducts a determination testsimilarly to the transition delay test in a manner that one of the fivedivided circuit blocks 21-a to 21-e operates at a time (two or morecircuit blocks do not concurrently operate) (a circuit scale of 20%).Next, the testing device 10 conducts a determination test in a mannerthat two of the five divided circuit blocks 21-a to 21-e operate at atime (a circuit scale of 40%). Hereinafter, the testing device 10similarly conducts a determination test in a manner that three (acircuit scale of 60%), four (a circuit scale of 80%), and five (acircuit scale of 100%) of the five divided circuit blocks 21-a to 21-eoperate in sequence.

The determination test similar to the transition delay test isrepeatedly conducted while gradually increasing the circuit scale asdescribed above, and the testing device 10 compares, every time onedetermination test is conducted, the changed signal (the operationresult of the internal circuit) to the expected value and determineswhether they coincide with each other or not (S3). As a result, when thechanged signal coincides with the expected value (OK), the testingdevice 10 accumulates the circuit scale operating at that time as thedetermination data (S4), and conducts a next determination test. On theother hand, when the changed signal does not coincide with the expectedvalue (NG) or when the test is finished at the whole circuit scale (thecircuit scale of 100%), the testing device 10 causes the detectioncircuit 23 in the semiconductor device 20 to perform data comparison(S5), and acquires the measurement result relating to the power supplynoise. Thus, the information relating to the power supply noise amountwith which the changed signal does not coincide with the expected valuecan be acquired in the transition delay test.

Next, the testing device 10 determines the circuit scale on which thetransition delay test can be normally conducted without being affectedby the influence of the power supply noise, based on the result obtainedby the aforementioned operation (the accumulated determination data andthe measurement result relating to the power supply noise acquired fromthe detection circuit 23) (S6). For example, when the determination isNG in the determination test with the concurrently operating circuitscale set to 40%, the testing device 10 decides to limit theconcurrently operating circuit scale in the transition delay test to20%, and when the determination is NG in the determination test with theconcurrently operating circuit scale set to 80%, the testing device 10decides to limit the concurrently operating circuit scale in thetransition delay test to 60%.

Subsequently, the testing device 10 limits the concurrently operatingcircuit scale in the transition delay test to the circuit scale decidedat step S6, namely, sets the concurrently operating circuit scale not toexceed the decided circuit scale decided at step S6, and conducts thetransition delay test of the semiconductor 20 (S7). For example, whenthe concurrently operating circuit scale is limited to 20%, thetransition delay test is conducted such that the clock control circuit22 controls the clocks to be supplied to the circuit blocks 21-a to 21-eso that one of the circuit blocks 21-a to 21-e operates at a time (twoor more of the circuit blocks do not concurrently operate). For example,by supplying clocks to the circuit blocks 21-a to 21-e with the phasesbeing made different from one another as illustrated in FIG. 3C, thecircuit blocks 21-a to 21-e can be controlled to operate one by one.Further, the control of supplying the clock only to one circuit blockand interrupting the clocks to the other circuit blocks is conducted foreach of the circuit blocks 21-a to 21-e, whereby the circuit blocks 21-ato 21-e can be controlled to operate one by one.

Further, for example, when the concurrently operating circuit scale islimited to 60%, the transition delay test is conducted such that theclock control circuit 22 controls the clocks to be supplied to thecircuit blocks 21-a to 21-e to cause three circuit blocks (for example,the circuit block 21-a, 21-b, 21-c) of the circuit blocks 21-a to 21-eto concurrently operate and the remaining two circuit blocks (forexample, the circuit blocks 21-d, 21-e) to concurrently operate. Forexample, the phases of the three clocks of the clocks to be supplied tothe circuit blocks 21-a to 21-e are synchronized and the phases of theremaining two clocks are synchronized shifted from the phases of thethree clocks, whereby the concurrently operating circuit scale can belimited to 60%. Further, for example, by controlling supply/interruptionof the clocks as illustrated in FIG. 4A and FIG. 4B, the concurrentlyoperating circuit scale can be limited to 60%.

Note that the above-explained clock control example is one example, andthe clock control is not limited to this example.

The testing device 10 then conducts test until conduction of thetransition delay test to the whole internal circuit 21 of thesemiconductor device 20, namely, all of the circuit blocks 21-a to 21-eis completed, and ends the operation when conduction of the transitiondelay test to the whole internal circuit 21 is completed (S8).

According to this embodiment, a determination test is conducted with theconcurrently operating circuit blocks (the flip-flop number) beingchanged to determine an appropriate circuit scale on which thetransition delay test can be normally conducted without being affectedby the influence of the power supply noise as a result of thedetermination test and a measurement result relating to the power supplynoise generated during the conduction of the determination test. Then,the concurrently operating circuit scale in the transition delay test islimited not to exceed the appropriate circuit scale obtained by thedetermination, and the transition delay test to the semiconductor device20 is conducted. This makes it possible to conduct the transition delaytest with the appropriate circuit scale on which the test can benormally conducted without being affected by the influence of the powersupply noise, and to suppress occurrence of inconvenience that asemiconductor device 20 that will be determined as non-defective withoutinfluence of the noise is determined as defective due to the influenceof the noise.

Further, the transition delay test is not conducted with the internalcircuit 21 of the semiconductor device 20 being just divided, but thetransition delay test can be conducted with the appropriate circuitscale on which the test can be normally conducted, so that thetransition delay test can be efficiently conducted on the wholesemiconductor device 20. For example, when the total number of thecircuit blocks on which the transition delay test has not been conductedin the internal circuit 21 is equal to or more than the circuit scalethat has been determined to be normally subjected to the test, theclocks are controlled so that the circuit scale becomes equal to theconcurrently operating circuit blocks in the transition delay test. Thismakes it possible to conduct the transition delay test on the wholesemiconductor device 20 at a smallest number of execution times.

Note that the case where the internal circuit 21 of the semiconductordevice 20 is divided into five circuit blocks is illustrated as anexample in the above explanation, the division number is not limited tothis. The division number of the internal circuit 21 is arbitrary, andthe configuration of the determination part 31 and the like of thedetection circuit 23 may be changed as necessary according to thedivision number of the internal circuit 21. Further, in this embodiment,the internal circuit 21 of the semiconductor device 20 is divided intofive blocks, and the circuit scale suitable for conduction of thetransition delay test is decided while the concurrently operatingcircuit scale is changed to 20%, 40%, 60%, 80%, 100%. However, notlimited to this, the concurrently operating circuit scale suitable forconduction of the transition delay test may be decided, for example,while the concurrently operating circuit scale is changed to 20%, 60%,100%.

A disclosed semiconductor device test method achieves the effect capableof determining an appropriate circuit scale on which the operation testcan be normally conducted without being affected by influence of a powersupply noise, based on a result of the determination test conducted withthe concurrently operating circuit blocks changed and the power supplynoise generated during the conduction of the determination test, andconducting an operation test on a test object circuit.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiment of the presentinvention has been described in detail, it should be understood that thevarious changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

1. A semiconductor device test method, comprising: conducting adetermination test of a test object circuit in a semiconductor devicedivided into a plurality of circuit blocks, while changing concurrentlyoperating circuit blocks; detecting a power supply noise generated inthe semiconductor device during conduction of the determination test;determining a circuit scale relating to conduction of an operation testbased on a result of the determination test conducted in the conductingand the power supply noise detected in the detecting; and performing theoperation test on the test object circuit controlling clocks to besupplied to the circuit blocks so that the circuit scale of theconcurrently operating circuit blocks does not exceed the circuit scaledetermined in the determining.
 2. The semiconductor device test methodaccording to claim 1, wherein in the performing the operation test,phases of the clocks to be supplied to the circuit blocks are adjustedso that the circuit scale of the concurrently operating circuit blocksdoes not exceed the circuit scale determined in the determining.
 3. Thesemiconductor device test method according to claim 1, wherein in theperforming the operation test, supply and interruption of the clock toeach of the circuit blocks are controlled so that the circuit scale ofthe concurrently operating circuit blocks does not exceed the circuitscale determined in the determining.
 4. The semiconductor device testmethod according to claim 1, wherein in the performing the operationtest, the clocks to be supplied to the circuit blocks so that thecircuit scale of the concurrently operating circuit blocks is equal tothe circuit scale determined in the determining when the circuit scaleon which the operation test has not been conducted of the test objectcircuit is equal to or more than the circuit scale determined in thedetermining.
 5. The semiconductor device test method according to claim1, wherein in the detecting, the power supply noise is detected bycomparing a comparison voltage generated based on a reference powersupply and a power supply voltage of the semiconductor device duringconduction of the determination test.
 6. The semiconductor device testmethod according to claim 1, wherein the circuit scale of each of thecircuit blocks is the same.
 7. The semiconductor device test methodaccording to claim 1, wherein the test object circuit is divided intothe plurality of circuit blocks so that the numbers of flip-flopsincluded in the circuit blocks are substantially equal.
 8. Asemiconductor device, comprising: a test object circuit divided into aplurality of circuit blocks; a detection circuit detecting a powersupply noise generated during conduction of a test on the test objectcircuit; and a clock control circuit controlling a clock to be suppliedto each of the circuit blocks in conducting the test, according to thenumber of concurrently operable circuit blocks decided based on thepower supply noise detected by the detection circuit.
 9. Thesemiconductor device according to claim 8, wherein the clock controlcircuit adjusts phases of the clocks to be supplied to the circuitblocks according to the decided number of concurrently operable circuitblocks.
 10. The semiconductor device according to claim 9, wherein theclock control circuit shifts the phases of the clocks to be supplied tothe circuit blocks so that the number of circuit blocks havingsynchronized phases of the supplied clocks is equal to or less than thedecided number of the concurrently operable circuit blocks.
 11. Thesemiconductor device according to claim 9, wherein the clock controlcircuit has a plurality of delay devices each disposed to each of thecircuit blocks and capable of independently controlling a delay amount,and wherein the delay device delays an inputted clock by the delayamount and outputs a delayed clock to the corresponding circuit block.12. The semiconductor device according to claim 9, wherein the clockcontrol circuit has a plurality of sets of a delay device and a selectordisposed to the circuit blocks respectively, wherein the delay devicedelays an inputted clock by a set delay amount and outputs a delayedclock, and wherein the selector, into which the clock and the delayedclock are inputted, outputs one of the clock and the delayed clock tothe corresponding circuit block according to control from an externalpart.
 13. The semiconductor device according to claim 8, wherein theclock control circuit controls supply and interruption of the clock toeach of the circuit blocks according to the decided number ofconcurrently operable circuit blocks.
 14. The semiconductor deviceaccording to claim 13, wherein the clock control circuit has gatecircuits each disposed to each of the circuit blocks and switchingbetween supply and interruption of the clock to the correspondingcircuit block.
 15. A semiconductor device test method, comprising:determining a circuit scale relating to conduction of an operation testbased on a result of a determination test of a test object circuit in asemiconductor device divided into a plurality of circuit blocksconducted while changing concurrently operating circuit blocks and apower supply noise detected in the semiconductor device duringconduction of the determination test; and performing the operation teston the test object circuit outputting a control signal relating tocontrol of clocks to be supplied to the circuit blocks so that thecircuit scale of the concurrently operating circuit blocks does notexceed the circuit scale determined in the determining.